Gate-Induced Fermi Level Tuning in InP Nanowires at Efficiency Close to the Thermal Limit.
Summary, in English
As downscaling of semiconductor devices continues, one or a few randomly placed dopants may dominate the characteristics. Furthermore, due to the large surface-to-volume ratio of one-dimensional devices, the position of the Fermi level is often determined primarily by surface pinning, regardless of doping level. In this work, we investigate the possibility of tuning the Fermi level dynamically with wrap-around gates, instead of statically setting it using the impurity concentration. This is done using Ω-gated metal-oxide-semiconductor field-effect transistors with HfO(2)-capped InP nanowires as channel material. It is found that induced n-type devices exhibit an optimal inverse subthreshold slope of 68 mV/decade. By adjusting the growth and process parameters, it is possible to produce ambipolar devices, in which the Fermi level can be tuned across the entire band gap, making it possible to induce both n-type and p-type conduction.
- Solid State Physics
- NanoLund: Center for Nanoscience
The American Chemical Society (ACS)
- Nano Technology
- ISSN: 1530-6992