Your browser has javascript turned off or blocked. This will lead to some parts of our website to not work properly or at all. Turn on javascript for best performance.

The browser you are using is not supported by this website. All versions of Internet Explorer are no longer supported, either by us or Microsoft (read more here: https://www.microsoft.com/en-us/microsoft-365/windows/end-of-ie-support).

Please use a modern browser to fully experience our website, such as the newest versions of Edge, Chrome, Firefox or Safari etc.

Portrait of Erik Lind; Photo: Kennet Ruona

Erik Lind

Professor, Coordinator Nanoelectronics & Nanophotonics

Portrait of Erik Lind; Photo: Kennet Ruona

Fabrication of Tunnel FETs demonstrating sub-thermal subthreshold slope

Author

  • Abinaya Krishnaraja
  • Johannes Svensson
  • Erik Lind
  • Lars-Erik Wernersson

Summary, in English

Tunnel Field Effect Transistor (TFET), based on band-to-band tunneling, overcomes the thermal limit (subthreshold slope (S) > 60 mV/decade) of the MOSFETs by filtering the high-energy Fermi tail, thereby allowing a substantial reduction of supply voltage and power consumption. Despite the steep slope behavior, TFETs can suffer from ambipolarity wherein carriers tunnel into the channel at both high positive and negative gate voltages. In this work, we demonstrate the fabrication of InAs/InGaAsSb/GaSb vertical nanowire TFET devices and present experimental data showcasing suppressed ambipolarity and a minimum S = 39 mV/decade at Vds=0.05V. The nanowires were grown using MOVPE where the 100nm long InAs drain was n-doped with TESn followed by a 100nm undoped InAs channel and a 100nm/300nm DEZn doped InGaAsSb/GaSb source. After growth, the InAs was selectively digitally etched using citric acid to reduce the channel diameter from 40nm to 25nm. The electrostatics was improved, compared to our previously reported devices, with a gate stack of ALD bilayer of 1nm/3nm Al2O3/HfO2 (EOT~1nm) followed by 30nm sputtered W. To decrease the ambipolar conduction, a gate-drain underlap of approximately 20nm was used which widens the tunnel barrier at the drain junction. Since the gate length is defined by the bottom spacer thickness in vertical transistors, the underlap provides a shorter gate positioned close to the source-channel junction. Thus the new process scheme has improved the slope and reduced the OFF current by one order of magnitude compared to our previous devices [1].


[1] E. Memisevic et al., IEEE Trans.ElectronDevices,vol.64,4746–4751, 2017.

Department/s

  • Nano Electronics
  • NanoLund

Publishing year

2019-07-01

Language

English

Document type

Conference paper: abstract

Topic

  • Other Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

21th International Vacuum Congress

Conference date

2019-07-01 - 2019-07-05

Conference place

Malmö, Sweden

Status

Published

Research group

  • Nano Electronics