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Portrait of Erik Lind; Photo: Kennet Ruona

Erik Lind

Professor, Coordinator Nanoelectronics & Nanophotonics

Portrait of Erik Lind; Photo: Kennet Ruona

Capacitance Scaling in In0.71Ga0.29As/InP MOSFETs with Self-Aligned a:Si Spacers

Author

  • Navya S. Garigapati
  • Fredrik Lindelow
  • Lasse Sodergren
  • Erik Lind

Summary, in English

In0.71Ga0.29As/InP (12/2 nm) quantum well MOSFETs using sacrificial amorphous silicon (a:Si) spacers to achieve low parasitic capacitance are fabricated. Radio frequency characterization of 73 devices is used to study the intrinsic and extrinsic capacitances. The total gate intrinsic parasitic capacitance of 0.55 fF/μm is achieved with an intrinsic gate capacitance of 0.39 μF/cm2. The various parasitic capacitances are modeled using finite element electrostatic simulations, and semi-analytical expressions are provided. A device with a gate length Lg=80 nm has SS min=168 mV/dec, dc transconductance gm,e =1.0 mS μ m at VDS=0.5 V, and exhibits a peak cutoff frequency it fT of 243 GHz, and a maximum oscillation frequency it fmax of 147 GHz at VGS=0.25 V, VDS= 1 V.

Department/s

  • Nano Electronics
  • NanoLund

Publishing year

2021

Language

English

Pages

3762-3767

Publication/Series

IEEE Transactions on Electron Devices

Volume

68

Issue

8

Document type

Journal article

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • amorphous silicon (a:Si)
  • capacitance
  • hydrogen silsesquioxane (HSQ)
  • III-V compound semiconductor
  • MOSFET

Status

Published

Research group

  • Nano Electronics

ISBN/ISSN/Other

  • ISSN: 0018-9383