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Portrait of Erik Lind; Photo: Kennet Ruona

Erik Lind

Professor, Coordinator Nanoelectronics & Nanophotonics

Portrait of Erik Lind; Photo: Kennet Ruona

A Method for Determining Trap Distributions of Specific Channel Surfaces in InGaAs Tri-gate MOSFETs

Author

  • Seiko Netsu
  • Markus Hellenbrand
  • Cezar B. Zota
  • Yasuyuki Miyamoto
  • Erik Lind

Summary, in English

We present a method for estimating the trap distributions on each of the surfaces in a multi-gate MOSFET. We perform I-V hysteresis measurements on InGaAs Tri-gate MOSFETs with various channel widths (25, 60 and 100 nm) from which top surface and side wall trap distributions are determined. We show that the total trap distribution of a device can be expressed as a linear combination of the top surface and side wall trap distributions. The results show that the minimum trap density of the top InGaAs (100) surface is smaller than that of the 110 side walls by almost an order of magnitude. Since the nanowire constituting the channel in these devices is selectively regrown, rather than etched out, the different trap distributions can be explained by the specific surface chemistries of two surfaces.

Department/s

  • Nano Electronics
  • NanoLund
  • Department of Electrical and Information Technology

Publishing year

2018-02-16

Language

English

Pages

408-412

Publication/Series

IEEE Journal of the Electron Devices Society

Volume

6

Document type

Journal article

Publisher

Institute of Electrical and Electronics Engineers Inc.

Topic

  • Other Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Electron traps
  • FinFETs.
  • high-κ
  • Hysteresis
  • hysteresis
  • III-V
  • InGaAs
  • inter face trap
  • Logic gates
  • Mathematical model
  • MOSFET
  • MOSFETs
  • Multi-gate
  • Surface fitting
  • Surface treatment
  • trap density

Status

Published

Research group

  • Nano Electronics

ISBN/ISSN/Other

  • ISSN: 2168-6734