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Portrait of Erik Lind; Photo: Kennet Ruona

Erik Lind

Professor, Coordinator Nanoelectronics & Nanophotonics

Portrait of Erik Lind; Photo: Kennet Ruona

Capacitance Measurements in Vertical III-V Nanowire TFETs

Author

  • Markus Hellenbrand
  • Elvedin Memisevic
  • Johannes Svensson
  • Abinaya Krishnaraja
  • Erik Lind
  • Lars-Erik Wernersson

Summary, in English

By measuring scattering parameters over a wide range of bias points, we study the intrinsic gate capacitance as well as the charge partitioning of vertical nanowire tunnel field-effect transistors (TFETs). The gate-to-drain capacitance Cgd is found to largely dominate the on-state of TFETs, whereas the gate-to-source capacitance Cgs is sufficiently small to be completely dominated by parasitic components. This indicates that the tunnel junction on the source side almost completely decouples the channel charge from the small-signal variation in the source, while the absence of a tunnel junction on the drain side allows the channel charge to follow the drain small-signal variation much more directly.

Department/s

  • Department of Electrical and Information Technology
  • Nano Electronics

Publishing year

2018-05-04

Language

English

Pages

943-946

Publication/Series

IEEE Electron Device Letters

Volume

39

Issue

7

Document type

Journal article (letter)

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Other Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Vertical Nanowires
  • III-V
  • TFET
  • Small-signal model
  • Intrinsic Capacitance
  • RF
  • Cgd
  • Cgs

Status

Published

Research group

  • Nano Electronics

ISBN/ISSN/Other

  • ISSN: 0741-3106