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Portrait of Erik Lind; Photo: Kennet Ruona

Erik Lind

Professor, Coordinator Nanoelectronics & Nanophotonics

Portrait of Erik Lind; Photo: Kennet Ruona

Comparison of Low-Frequency Noise in Nanowire and Planar III-V MOSFETs

Author

  • Markus Hellenbrand
  • Olli-Pekka Kilpi
  • Johannes Svensson
  • Erik Lind
  • Lars-Erik Wernersson

Summary, in English

We compare III-V nanowire (NW) metal-oxidesemiconductor field-effect transistors (MOSFETs) in a vertical gate-all-around (GAA) as well as a lateral trigate architecture with planar reference MOSFETs and reveal that the NW geometry does not deteriorate the low-frequency noise (LFN) performance. In fact, with gate oxides deposited at the same conditions, the NW structures show potential to achieve better metrics due to slightly lower border trap densities Nbt. The normalized LFN in transistors with a higher number of NW can degrade due to averaging effects between individual nanowires within the same device.

Department/s

  • Department of Electrical and Information Technology
  • Nano Electronics
  • NanoLund

Publishing year

2019-07-02

Language

English

Document type

Conference paper

Topic

  • Other Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Low-Frequency Noise
  • MOSFETs
  • Nanowires (NWs)

Conference name

Insulating Films on Semiconductors (INFOS)

Conference date

2019-06-30 - 2019-07-03

Conference place

Cambridge, United Kingdom

Status

Published

Research group

  • Nano Electronics