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Portrait of Erik Lind; Photo: Kennet Ruona

Erik Lind

Professor, Coordinator Nanoelectronics & Nanophotonics

Portrait of Erik Lind; Photo: Kennet Ruona

Junctionless tri-gate InGaAs MOSFETs

Author

  • Cezar B. Zota
  • Mattias Borg
  • Lars Erik Wernersson
  • Erik Lind

Summary, in English

We demonstrate and characterize junctionless tri-gate InGaAs MOSFETs, fabricated using a simplified process with gate lengths down to L g = 25 nm at a nanowire dimension of 7 - 16 nm2. These devices use a single 7-nm-thick In0.80Ga0.20As (N D = 1 - 1019 cm-3) layer as both channel and contacts. The devices show SSsat = 76 mV/dec, peak g m = 1.6 mSm and I ON = 160A/m (at I OFF = 100 nA/m and V DD = 0.5 V), the latter which is the highest reported value for a junctionless FET. We also show that device performance is mainly limited by high parasitic access resistance due to the narrow and thin contact layer.

Department/s

  • Nano Electronics
  • NanoLund

Publishing year

2017-12-01

Language

English

Publication/Series

Japanese Journal of Applied Physics

Volume

56

Issue

12

Document type

Journal article

Publisher

IOP Publishing

Topic

  • Other Electrical Engineering, Electronic Engineering, Information Engineering

Status

Published

Project

  • Integration of III-V Nanowire Semiconductors for next Generation High Performance CMOS SOC Technologies

Research group

  • Nano Electronics

ISBN/ISSN/Other

  • ISSN: 0021-4922