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Portrait of Erik Lind; Photo: Kennet Ruona

Erik Lind

Professor, Coordinator Nanoelectronics & Nanophotonics

Portrait of Erik Lind; Photo: Kennet Ruona

Modelling and optimization of III/V transistors with matrices of nanowires

Author

  • Christian Larsen
  • Mats Ärlelid
  • Erik Lind
  • Lars-Erik Wernersson

Summary, in English

The magnitude and Impact of the parasitic capacitances in a vertical InAs nanowire transistor consisting of a matrix of nanowires is evaluated A simple transistor model is fitted to experimental I-V characteristics and the influence of the parasitic components on the transistor performance for different structures is investigated Simulations of the S parameters indicate an intrinsic f(T) of about 690 GHz for 50 nm L-G We show that f(T) reaches 56% of the intrinsic value in an optimized transistor structure with closely spaced nanowires and that a high wire density is more efficient to reduce the parasitics than to pattern the electrodes Finally the analytical model is used to demonstrate the operation and to simulate the performance of ring-oscillators (C) 2010 Elsevier Ltd All rights reserved

Department/s

  • Department of Electrical and Information Technology
  • Solid State Physics
  • NanoLund

Publishing year

2010

Language

English

Pages

1505-1510

Publication/Series

Solid-State Electronics

Volume

54

Issue

12

Document type

Journal article

Publisher

Elsevier

Topic

  • Condensed Matter Physics
  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Wrap gate
  • InAs
  • Ring oscillator
  • Nanowire
  • Field Effect Transistor

Status

Published

Research group

  • Nano

ISBN/ISSN/Other

  • ISSN: 0038-1101