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Portrait of Erik Lind; Photo: Kennet Ruona

Erik Lind

Professor, Coordinator Nanoelectronics & Nanophotonics

Portrait of Erik Lind; Photo: Kennet Ruona

Stacking of heterostructures and metallic elements for a submicron resonant tunneling transistor

Author

  • Erik Lind
  • Peter Lindström
  • I. Pietzonka
  • Werner Seifert
  • Lars-Erik Wernersson

Summary, in English

We have successfully embedded a metal gate in-between two resonant tunneling double barrier heterostructures (RTD), thus realizing a three dimensional resonant tunneling transistor. The gate is placed 30 nm above and 100 below the two RTD's, respectively. The asymmetric gate allows for a unique control of the current-voltage characteristics, not only controlling the peak current but also the peak voltage. We have modeled the transistor with Cadence, a standard simulation package for circuit simulations, achieving good agreement with experimental data

Department/s

  • Department of Electrical and Information Technology
  • Solid State Physics

Publishing year

2002

Language

English

Publication/Series

7th International Conference on Nanometer-Scale Science and Technology and 21st European Conference on Surface Science

Document type

Conference paper

Publisher

Lund University

Topic

  • Condensed Matter Physics
  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • circuit simulations
  • peak voltage
  • simulation package
  • stacking
  • peak current
  • heterostructures
  • metallic elements
  • submicron resonant tunneling transistor
  • metal gate
  • resonant tunneling double barrier heterostructures
  • three dimensional resonant tunneling transistor
  • current-voltage characteristics
  • asymmetric gate
  • 30 to 100 nm
  • W-GaAs

Conference name

Proceedings of 7th International Conference on Nanometer-Scale Science and Technology and 21st European Conference on Surface Science (NANO-7/ECOSS-21)

Conference date

2002-06-24 - 2002-06-28

Conference place

Malmö, Sweden

Status

Published