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Portrait of Erik Lind; Photo: Kennet Ruona

Erik Lind

Professor, Coordinator Nanoelectronics & Nanophotonics

Portrait of Erik Lind; Photo: Kennet Ruona

Modeling of n-InAs metal oxide semiconductor capacitors with high-kappa gate dielectric

Author

  • Aein Shiri Babadi
  • Erik Lind
  • Lars-Erik Wernersson

Summary, in English

A qualitative analysis on capacitance-voltage and conductance data for high-kappa/InAs capacitors is presented. Our measured data were evaluated with a full equivalent circuit model, including both majority and minority carriers, as well as interface and border traps, formulated for narrow band gap metal-oxide-semiconductor capacitors. By careful determination of interface trap densities, distribution of border traps across the oxide thickness, and taking into account the bulk semiconductor response, it is shown that the trap response has a strong effect on the measured capacitances. Due to the narrow bandgap of InAs, there can be a large surface concentration of electrons and holes even in depletion, so a full charge treatment is necessary. (C) 2014 AIP Publishing LLC.

Department/s

  • Department of Electrical and Information Technology
  • NanoLund

Publishing year

2014

Language

English

Publication/Series

Applied Physics Reviews

Volume

116

Issue

21

Document type

Journal article

Publisher

American Institute of Physics (AIP)

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Status

Published

ISBN/ISSN/Other

  • ISSN: 1931-9401