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Portrait of Erik Lind; Photo: Kennet Ruona

Erik Lind

Professor, Coordinator Nanoelectronics & Nanophotonics

Portrait of Erik Lind; Photo: Kennet Ruona

Low-Frequency Noise in Nanowire and Planar III-V MOSFETs


  • Markus Hellenbrand
  • Olli-Pekka Kilpi
  • Johannes Svensson
  • Erik Lind
  • Lars-Erik Wernersson

Summary, in English

Nanowire geometries are leading contenders for future low-power transistor design. In this study, low-frequency noise is measured and evaluated in highly scaled III-V nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs) and in planar III-V MOSFETs to investigate to what extent the device geometry affects the noise performance. Number fluctuations are identified as the dominant noise mechanism in both architectures. In order to perform a thorough comparison of the two architectures, a discussion of the underlying noise model is included. We find that the noise performance of the MOSFETs in a nanowire architecture is at least comparable to the planar devices. The input-referred voltage noise in the nanowire devices is superior by at least a factor of four.


  • Department of Electrical and Information Technology
  • Nano Electronics
  • NanoLund

Publishing year





Microelectronic Engineering

Document type

Journal article




  • Nano Technology


  • III-V
  • Nanowire (NW)
  • Low-Frequency Noise
  • Gate Oxide Defects
  • Border Traps



Research group

  • Nano Electronics


  • ISSN: 0167-9317