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Portrait of Erik Lind; Photo: Kennet Ruona

Erik Lind

Professor, Coordinator Nanoelectronics & Nanophotonics

Portrait of Erik Lind; Photo: Kennet Ruona

Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs

Author

  • Olli Pekka Kilpi
  • Johannes Svensson
  • Erik Lind
  • Lars Erik Wernersson

Summary, in English

Vertical InAs/InGaAs nanowire MOSFETs are fabricated in a gate-last fabrication process, which allows gate-lengths down to 25 nm and accurate gate-alignment. These devices demonstrate high performance with transconductance of 2.4 mS/μm, high on-current, and off-current below 1 nA/μm. An in-depth analysis of the heterostructure MOSFETs are obtained by systematically varying the gate-length and gate location. Further analysis is done by using virtual source modeling. The injection velocities and transistor metrics are correlated with a quasi-ballistic 1-D MOSFET model. Based on our analysis, the observed performance improvements are related to the optimized gate-length, high injection velocity due to asymmetric scattering, and low access resistance.

Department/s

  • Nano Electronics
  • NanoLund

Publishing year

2019

Language

English

Pages

70-75

Publication/Series

IEEE Journal of the Electron Devices Society

Volume

7

Document type

Journal article

Publisher

Institute of Electrical and Electronics Engineers Inc.

Topic

  • Other Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Fabrication
  • heterostructure.
  • InAs
  • InGaAs
  • Logic gates
  • MOSFET
  • nanowire
  • Resistance
  • Scattering
  • Semiconductor device modeling
  • Vertical

Status

Published

Research group

  • Nano Electronics

ISBN/ISSN/Other

  • ISSN: 2168-6734