Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si
Summary, in English
In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on-and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.
- Department of Electrical and Information Technology
Technical Digest - International Electron Devices Meeting, IEDM
Institute of Electrical and Electronics Engineers Inc.
- Electrical Engineering, Electronic Engineering, Information Engineering
61st IEEE International Electron Devices Meeting, IEDM 2015
2015-12-07 - 2015-12-09
Washington, United States
- ISBN: 9781467398930