Block Copolymer Nanopatterning of Dielectric Mask for Selective Area InAs Vertical Nanowire Growth
Summary, in English
Our study uses polystyrene-block-poly(4-vinyl pyridine) (PS-b-P4VP) nanopatterning of a dielectric mask, a thin layer (5-23 nm) of Silicon Nitride or Silicon Dioxide, on top of an epitaxially grown InAs layer on Si(111). Based upon Park et al. , we performed the spin-coating from a 0.625 wt% solution of PS50k-b-P4VP17k in Toluene:Tetrahydrofuran (THF) (4:1 volume ratio). After exploring microphase separation using various solvent ratios, our samples have been annealed in a solvent vapor mixture of THF and Methanol (9:1 volume ratio) for 4 hours in room temperature, resulting in formation of a hexagonal pattern of P4VP cylinders at 50 nm pitch in a PS matrix. Immersion into a preferential solvent for P4VP, such as Ethanol, extracts the P4VP to the surface, and opens up pores in the BCP . Our study shows, that the pore diameter can thereafter be tuned by changing the temperature of Ethanol immersion (see Fig. 1a), suggesting that the mask opening diameters, and therefore also the nanowire diameters, is possible to tune in this way.
Oxygen plasma reactive ion etching thereafter removed any polymer residuals at the bottom of the structures, whereas CF4/CHF3 plasma transferred the structures into the dielectric layer. After wet etching of the native oxide, InAs nanowires were grown from the 50 nm pitch openings in the dielectric layer in MOVPE (see Fig. 1b-c). A more detailed study of the effects of process conditions, epitaxial V/III precursor ratio and growth temperature on NW growth is underway.
Figure 1. a) Graph of SEM analyzed pore diameter as a function of temperature after 1 hour Ethanol immersion, b) SEM top view image of PS-b-P4VP mask after transferring the pattern into the silicon dioxide layer on top of InAs/Si(111), and c) SEM tilted view image of InAs nanowires grown from openings in the silicon dioxide layer on top of InAs/Si(111).
We acknowledge B. Landeke-Wilsmark for his contributions in the initial stages of this work. All nanofabrication was carried out in Lund Nano Lab. We acknowledge financial support from the Swedish Foundation for Strategic Research, project SSF RIF14-0090. The work was also supported by NanoLund and MyFab.
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- Solid State Physics
- Nano Electronics
Conference paper: abstract
- Nano Technology
4-th International Symposium on DSA, November 11-13, 2018, Sapporo, Japan
2018-11-11 - 2018-11-13
- Nano Electronics