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Portrait of Reine Wallenberg. Photo: Kennet Ruona

Reine Wallenberg

Professor, Coordinator Materials Science

Portrait of Reine Wallenberg. Photo: Kennet Ruona

High-Performance Vertical III-V Nanowire MOSFETs on Si with gm> 3 mS/μm

Author

  • Olli Pekka Kilpi
  • Markus Hellenbrand
  • Johannes Svensson
  • Axel R. Persson
  • Reine Wallenberg
  • Erik Lind
  • Lars Erik Wernersson

Summary, in English

Vertical III-V nanowire MOSFETs have demonstrated excellent performance including high transconductance and high Ion. One main bottleneck for the vertical MOSFETs is the large access resistance arising from the contacts and ungated regions. We demonstrate a process to reduce the access resistance by combining a gate-last process with ALD gate-metal deposition. The devices demonstrate fully scalable gm down to Lg = 25 nm. These vertical core/shell InAs/InGaAs MOSFETs demonstrate gm = 3.1 mS/μm and Ron = 190 Ωμm. This is the highest gm demonstrated on Si. Transmission line measurement verifies a low contact resistance with RC = 115 Ωμm, demonstrating that most of the MOSFET access resistance is located in the contact regions.

Department/s

  • Nano Electronics
  • Centre for Analysis and Synthesis
  • NanoLund

Publishing year

2020

Language

English

Pages

1161-1164

Publication/Series

IEEE Electron Device Letters

Volume

41

Issue

8

Document type

Journal article

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Nano Technology
  • Other Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • InAs
  • InGaAs
  • MOSFET
  • nanowire
  • TLM
  • Vertical

Status

Published

Research group

  • Nano Electronics

ISBN/ISSN/Other

  • ISSN: 0741-3106