Jun
Seminar with Dr Bernadette Kunert: III-V Nano-Ridge Engineering for Device Integration to 300 mm Si Substrates
We have the pleasure to have Dr Bernardette Kunert, Principal Scientist at IMEC, to visit Lund for the dissertation of Heera Menon. Dr Kunert has agreed to give a seminar about her very impressive research on III-V semiconductor device integration onto large scale 300 mm Si.
Abstract:
Nano-Ridge Engineering (NRE) is a novel method for integrating III-V devices to Si substrates. This approach utilizes selective area growth (SAG) through metal organic vapor phase epitaxy (MOVPE) on Si wafers that have been patterned with narrow Si/SiO2 trenches exhibiting a high aspect ratio (trench depth divided by trench width >> 3). These narrow trenches ensure effective trapping of misfit defects at the SiO2 sidewalls during SAG of III-V materials, which are introduced by the lattice mismatch with Si substrates. Such a defect confinement technique is commonly referred to as aspect ratio trapping (ART). Moreover, the bottom of the trenches is defined by two {111} Si facets, preventing the formation of anti-phase disorder and facilitating the strain relaxation in the III-V nucleation layer along the III-V/Si interface.
The important feature of NRE is the continuation of III-V growth beyond the trench boundaries to increase the volume of III-V material by forming a large nano-ridge (NR) above the oxide pattern for device integration. The shape, size, and extent of these NRs can be engineered by the applied MOVPE growth conditions. Therefore, by employing NRE, a substantial volume of high-quality III-V NRs can be achieved on top of narrow trenches, thereby taking advantage of efficient ART. Another benefit of NRE is the clear separation between the region of strain relaxation which occurs inside the trenches, and the device area, which is mainly defined by the NR on top of the pattern. This separation leads to improved device performance and lifetime.
After a brief introduction to the principles of NRE, this presentation will focus on different NR device demonstrations on 300 mm Si wafers out of the field of silicon photonics and advanced radio frequencies. Next to this, challenges and open questions related to NRE will be discussed comparing different III-V NR materials.
Welcome!
About the event
Location:
k-space
Contact:
mattias [dot] borg [at] eit [dot] lth [dot] se